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CoreFFT Fast Fourier Transform
Once the CoreFFT module has computed the FFT, the
results are written to the module’s output memory
buffer, and signal y_rdy is taken HIGH. Every output
sample is accompanied by a validity bit, y_valid , to
indicate to the receiving host that a valid output sample
is ready to be read from both b -bit output busses. The
receiving host can control the output sample rate using
the read_y input of the module. Asserting read_y
indicates to the FFT module that the receiving host is
ready to read samples. Deasserting read_y informs the
module that the host is not ready. Any unread samples
are held in the module’s output buffer until the host is
CoreFFT Device Requirements
Table 1 and Table 2 on page 4 provide typical utilization
and performance data for CoreFFT, which is
implemented in various Actel devices with the
configurations listed in Table 1 and Table 2 on page 4 .
Device utilization and performance will vary depending
upon the FFT parameters used. The transform size
parameter N primarily impacts the number of RAM
blocks and the time required for transformation. "FFT
Computation" on page 5 provides more details on how
the FFT time depends on the transform size.
ready.
Table 1 ? CoreFFT Device Utilization and Performance (bit width b = 16)
Cells or Tiles
Device
Clock
FFT
FPGA Family and
FFT
Utilization
RAM
Speed
Rate,
Time,
Device
ProASIC3/E A3P1000
Points
256
512
1,024
Comb.
5,325
6,105
6,904
Seq.
2,039
2,062
2,126
Total
7,364
8,167
9,030
%
29.96%
33.23%
36.74%
Blocks
14
14
28
Grade
–2
–2
–2
MHz
100
92
90
μsec
11
26
58
ProASIC
PLUS
APA1000
256
512
1,024
6,904
6,901
9,091
2,026
2,019
2,431
8,930
8,920
11,522
15.90%
15.80%
20.50%
28
28
56
Std
Std
Std
59
62
62
19
39
85
Axcelerator AX1000
RTAX-S RTAX1000S
256
512
1,024
256
512
1,024
3,398
3,601
3,863
3,407
3,596
3,881
2,373
2,380
2,404
2,370
2,381
2,397
5,771
5,981
6,267
5,777
5,977
6,278
31.81%
32.96%
34.54%
31.84%
32.94%
34.60%
7
14
28
7
14
28
–2
–2
–2
–1
–1
–1
130
120
105
107
90
76
9
20
50
10
27
69
Notes:
1. Auto-scaling (block floating point) is enabled in all cases.
2. The above data were obtained by typical synthesis and place-and-route methods. Other core parameter settings can result in
different utilization and performance values.
3. All memory buffers are RAM-block-based.
4. Timing constraints supplied with CoreFFT were used.
5. Timing-driven layout options were used, effort level 3, with no multiple passes.
v4.0
3
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